When the input of the first NOT gate is high, its output is low. At this time, the current path shown by the dotted line in the figure will be formed, and the voltage on the parasitic inductance at the ground of the first NOT gate is: V=L*di/dt
Here i is the transient current formed by the logic transition process. If the circuit switching process is very fast (transistor switching time in high-speed devices has been reduced to the picosecond level), di/dt will be a large value, and even a small parasitic inductance L will induce a large voltage across the inductor. V. For some large-scale logic chips, the ground pin is shared by a lot of internal transistors. If these transistors are switched on and off at the same time, a large transient current will be generated. Coupled with the extremely fast switching time, the induced voltage on the parasitic inductance will increase. big.