Therefore, voltage disturbances exist all around the chip, and decoupling must be uniformly decoupled over the entire chip area. If the 680pF capacitors in the above picture are placed on the upper part of the chip, due to the problem of decoupling radius, the voltage disturbance at the lower part of the chip cannot be decoupled well.
When installing the capacitor, pull a small lead from the pad and connect it to the power plane through vias, as well as the ground terminal. In this way, the current loop of the flow capacitor is: power plane->via->lead-out->pad->capacitor->pad->lead-out>via->ground plane, Figure 15 intuitively shows the current return path .