One thing planar, FinFET, and RibbonFET transistors have in common is that they all use CMOS technology, which, as mentioned above, consists of n-type (NMOS) and p-type (PMOS) transistors. CMOS logic became mainstream in the 1980s because it consumed significantly less current than alternative technologies, especially NMOS-only circuits. Less current also leads to higher operating frequencies and higher transistor density.
To date, all CMOS technologies have placed standard NMOS and PMOS transistor pairs side by side. But in a keynote presentation at the 2019 IEEE International Electron Devices Meeting (IEDM), Intel introduced the concept of 3D stacked transistors that place NMOS transistors on top of PMOS transistors. The following year, at IEDM 2020, Intel demonstrated the design of the first logic circuit using this 3D technology, the inverter. Combined with proper interconnects, the 3D stacked CMOS approach effectively halves the inverter footprint and doubles the area density, further pushing the limits of Moore’s Law.