The operation of each internal transistor is usually synchronized by the core clock or the on-chip peripheral clock. However, due to the difference in internal delay, the state transition of each transistor cannot be strictly synchronized. When some transistors have completed state transition, other transistors May still be in the conversion process. A gate circuit that is at a high level inside the chip will transmit power supply noise to the input portion of other gate circuits. If the gate circuit receiving the power supply noise is in the indeterminate state region of level conversion at this time, the power supply noise may be amplified and generate rectangular pulse interference at the output end of the gate circuit, thereby causing logic errors in the circuit. Noise at the chip’s external power pins propagates through internal gate circuits, and may also trigger state transitions in internal registers.