The difference between them is that it defines which edge of the clock pulse toggles the output signal, which edge samples the input signal, and the stable level value of the clock pulse (that is, whether the clock signal is high or low when the clock signal is invalid). Each mode is characterized by a pair of parameters called clock polarity CPOL and clock phase CPHA.
The master and slave devices must use the same operating mode – SCLK, CPOL and CPHA to function properly. If there are multiple slave devices and they use different working modes, the master device must re-modify the mode of the corresponding slave device when reading and writing different slave devices.