Please take a look the 3W and 3H principles. The 3W principle must be followed when wiring clock, reset, signals greater than 100M, several essential bus signals, and other signal lines. The vias on the link should be as far apart as feasible, and neither the current layer nor any adjacent layers have any lengthy parallel lines. few. There is a problem with the quantity of vias for high-speed signals. The number of vias for high-speed signals is typically governed by rigorous restrictions in some device instruction books. According to the consulting interconnection concept, adding additional vias to the inner layer in addition to the required pin fanout vias is strictly prohibited. They pierced 4 vias and routed 8G PCIE 3.0 traces without any issues.The distance between the trace layer and the reflow plane, or “H,” must be strictly met by the center distance of clocks and high-speed signals on the same layer. It is also advised that the signals on adjacent layers adhere to the 3H concept. There are tools to check in regards to the crosstalk issues mentioned above.