Customization of high-performance chips for autonomous driving
Since the autonomous driving algorithm is still highly uncertain, the chip solution needs to take into account the computing power requirements and flexibility of the current AI algorithm. The combination of GPU (graphics processing unit) + FPGA (field programmable logic gate array) is favored by most players ; At present, Baidu Apollo and Audi zFAS all adopt the combination mode of “GPU + FPGA” supplemented by MCU, CPU (central processing unit) and other computing units. When the autonomous driving technology route is relatively mature and has entered the stage of large-scale commercial use, the existing GPUs are also difficult to integrate and process more spatial information, and customized application-specific integrated circuits (ASICs) are required.