Suppose we are using the MII interface, the communication rate is 100Mb, the data width is 4bit, and the rate is 25M. In order to match the rate of 25MHz * 4bit = 100Mbit/s, after the PHY receives data from the MII interface, it will first perform a 4B3B conversion and increase the clock frequency to 33.33333MHz to maintain a bit rate of 100 Mbps.
After that, the PHY needs to perform the 3B2T operation again, and convert the 3 bits received each time into 2 ternary level values (the value range is -1, 0, 1). The specific correspondence is as shown in the table above. shown. There are 8 combinations of 3 bits (that is, the power of 2), and there are 9 combinations of two level values (that is, the square of 3), so the latter can cover the former. At this time, the clock cycle is still 33.333M, but two levels in each clock cycle can represent 3 bits, so the data rate at this time is still 100Mbit/s, and each level actually contains 1.5bit information.